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1 lt1375/lt1376 13756fd applicatio s u descriptio u features typical applicatio u 1.5a, 500khz step-down switching regulators constant 500khz switching frequency uses all surface mount components inductor size reduced to 5 h easily synchronizable saturating switch design: 0.4 ? effective supply current: 2.5ma shutdown current: 20 a cycle-by-cycle current limiting portable computers battery-powered systems battery charger distributed power the lt 1375/lt1376 are 500khz monolithic buck mode switching regulators. a 1.5a switch is included on the die along with all the necessary oscillator, control and logic circuitry. high switching frequency allows a considerable reduction in the size of external components. the topology is current mode for fast transient response and good loop stability. both fixed output voltage and adjustable parts are available. a special high speed bipolar process and new design techniques achieve high efficiency at high switching fre- quency. efficiency is maintained over a wide output cur- rent range by using the output to bias the circuitry and by utilizing a supply boost capacitor to saturate the power switch. a shutdown signal will reduce supply current to 20 a on both parts. the lt1375 can be externally syn- chronized from 580khz to 900khz with logic level inputs. the lt1375/lt1376 fit into standard 8-pin pdip and so packages, as well as a fused lead 16-pin so with much lower thermal resistance. full cycle-by-cycle short-cir- cuit protection and thermal shutdown are provided. standard surface mount external parts are used, includ- ing the inductor and capacitors. for low input voltage applications with 3.3v output, see lt1507. this is a functionally identical part that can operate with input voltages between 4.5v and 12v. 5v buck converter load current (a) 0 efficiency (%) 100 90 80 70 60 50 1.00 1375/76 ta02 0.25 0.50 0.75 1.25 v out = 5v v in = 10v l = 10 h efficiency vs load current boost lt1376-5 v in output** 5v, 1.25a * ripple current i out /2 ** increase l1 to 10 h for load currents above 0.6a and to 20 h above 1a ? for input voltage below 7.5v, some restrictions may apply. see applications information. input 6v ? to 25v 1375/76 ta01 c2 0.1 f c c 3.3nf d2 1n5818 c1 100 f, 10v solid tantalum c3* 10 f to 50 f d2 1n914 l1** 5 h v sw fb bias gnd v c default = on shdn + + , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
2 lt1375/lt1376 13756fd absolute m axi m u m ratings w ww u input voltage lt1375/lt1376 .................................................. 25v lt1375hv/lt1376hv ........................................ 30v boost pin voltage lt1375/lt1376 .................................................. 35v lt1375hv/lt1376hv ........................................ 40v shdn pin voltage ..................................................... 7v bias pin voltage ...................................................... 7v fb pin voltage (adjustable part) ............................ 3.5v fb pin current (adjustable part) ............................ 1ma sense voltage (fixed 5v part) .................................. 7v sync pin voltage ..................................................... 7v operating junction temperature range lt1375c/lt1376c ............................... 0 c to 125 c lt1375i/lt1376i ............................. 40 c to 125 c storage temperature range ................ 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c (note 1) package/order i n for m atio n w u u top view s package 16-lead plastic narrow so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd nc boost v in v sw bias nc gnd gnd nc v c fb/sense gnd shdn nc gnd order part number ja =50 c/ w with fused corner pins connected to ground plane or large lands 1 2 3 4 8 7 6 5 top view boost v in v sw bias n8 package 8-lead pdip s8 package 8-lead plastic so v c fb/sense gnd shdn ja = 100 c/ w (n8) ja = 120 c/ w to 150 c/w depending on pc board layout (s8) 1 2 3 4 8 7 6 5 top view v c fb/sense gnd sync n8 package 8-lead pdip s8 package 8-lead plastic so boost v in v sw shdn ja = 100 c/ w (n8) ja = 120 c/ w to 150 c/w depending on pc board layout (s8) lt1375cn8 lt1375cn8-5 lt1375in8 lt1375in8-5 lt1375cs8 lt1375cs8-5 lt1375hvcs8 lt1375is8 lt1375is8-5 lt1375hvis8 order part number lt1376cn8 lt1376cn8-5 lt1376in8 lt1376in8-5 lt1376cs8 lt1376cs8-5 lt1376hvcs8 lt1376is8 lt1376is8-5 lt1376hvis8 s8 part marking 1375 13755 1375hv 1375i 1375i5 375hvi 1376 13765 1376hv 1376i 1376i5 376hvi lt1376cs lt1376is lt1376hvcs lt1376hvis order part number s8 part marking order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts specified with wider operating temperature ranges.
3 lt1375/lt1376 13756fd electrical characteristics the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. t j = 25 c, v in = 15v, v c = 1.5v, boost open, switch open, unless otherwise noted. parameter conditions min typ max units reference voltage (adjustable) 2.39 2.42 2.45 v 2.36 2.48 v sense voltage (fixed 5v) 4.94 5.0 5.06 v 4.90 5.10 v sense pin resistance 71014 k ? reference voltage line regulation 5v v in 25v 0.01 0.03 %/ v 5v v in 30v (lt1375hv/lt1376hv) 0.01 0.03 %/v feedback input bias current 0.5 1.5 a error amplifier voltage gain v shdn = 1v (notes 2, 8) 200 400 error amplifier transconductance v shdn = 1v, ? i (v c ) = 10 a (note 8) 1500 2000 2700 mho 1100 3000 mho v c pin to switch current transconductance 2a/v error amplifier source current v shdn = 1v, v fb = 2.1v or v sense = 4.4v 150 225 320 a error amplifier sink current v shdn = 1v, v fb = 2.7v or v sense = 5.6v 2 ma v c pin switching threshold duty cycle = 0 0.9 v v c pin high clamp v shdn = 1v 2.1 v switch current limit v c open, v fb = 2.1v or v sense = 4.4v, v boost = v in + 5v dc 50% 1.50 2 3 a dc = 80% 1.35 3 a switch on resistance (note 7) i sw = 1.5a, v boost = v in + 5v 0.3 0.4 ? 0.5 ? maximum switch duty cycle v fb = 2.1v or v sense = 4.4v 86 93 % switch frequency v c set to give 50% duty cycle 460 500 540 khz 0 c t j 125 c 440 560 khz 440 570 khz switch frequency line regulation 5v v in 25v 0.05 0.15 %/ v 5v v in 30v (lt1375hv/lt1376hv) 0.05 0.15 %/v frequency shifting threshold on fb pin ? f = 10khz 0.8 1.0 1.3 v minimum input voltage (note 3) 5.0 5.5 v minimum boost voltage (note 4) i sw 1.5a 3 3.5 v boost current (note 5) v boost = v in + 5v i sw = 500ma 12 22 ma i sw = 1.5a 25 35 ma input supply current (note 6) v bias = 5v 0.9 1.4 ma output supply current (note 6) v bias = 5v 3.2 4.0 ma shutdown supply current v shdn = 0v, v in 25v, v sw = 0v, v c open 15 50 a 75 a v shdn = 0v, v in 30v, v sw = 0v, v c open (lt1375hv/lt1376hv) 20 75 a 100 a lockout threshold v c open 2.3 2.38 2.46 v
4 lt1375/lt1376 13756fd electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: gain is measured with a v c swing equal to 200mv above the low clamp level to 200mv below the upper clamp level. note 3: minimum input voltage is not measured directly, but is guaranteed by other tests. it is defined as the voltage where internal bias lines are still regulated so that the reference voltage and oscillator frequency remain constant. actual minimum input voltage to maintain a regulated output will depend on output voltage and load current. see applications information. note 4: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. note 5: boost current is the current flowing into the boost pin with the pin held 5v above input voltage. it flows only during switch-on time. note 6: input supply current is the bias current drawn by the input pin when the bias pin is held at 5v with switching disabled. output supply current is the current drawn by the bias pin when the bias pin is held at 5v. total input referred supply current is calculated by summing input supply current (i si ) with a fraction of output supply current (i so ): i tot = i si + (i so )(v out /v in )(1.15) with v in = 15v, v out = 5v, i si = 0.9ma, i so = 3.6ma, i tot = 2.28ma. for the lt1375, quiescent current is equal to: i tot = i si + i so (1.15) because the bias pin is internally connected to v in . for lt1375 or bias open circuit, input supply current is the sum of input + output supply currents. note 7: switch-on resistance is calculated by dividing v in to v sw voltage by the forced current (1.5a). see typical performance characteristics for the graph of switch voltage at other currents. note 8: transconductance and voltage gain refer to the internal amplifier exclusive of the voltage divider. to calculate gain and transconductance refer to sense pin on fixed voltage parts. divide values shown by the ratio v out /2.42. the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. t j = 25 c, v in = 15v, v c = 1.5v, boost open, switch open, unless otherwise noted. parameter conditions min typ max units shutdown thresholds v c open device shutting down 0.15 0.37 0.60 v device starting up 0.25 0.45 0.60 v v c open lt1375hv/lt1376hv device shutting down 0.15 0.37 0.70 v lt1375hv/lt1376hv device starting up 0.25 0.45 0.70 v minimum synchronizing amplitude (lt1375 only) v in = 5v 1.5 2.2 v synchronizing range (lt1375 only) 580 900 khz sync pin input resistance 40 k ? inductance ( h) 05 core loss (w) core loss (% of 5w load) 1.0 0.1 0.01 0.001 10 15 20 20 12 8 4 2 1.2 0.8 0.4 0.2 0.12 0.08 0.04 0.02 25 1375/76 g01 type 52 powdered iron kool m permalloy = 125 v out = 5v, v in = 10v, i out = 1a core loss is independent of load current until load current falls low enough for circuit to go into discontinuous mode inductor core loss typical perfor m a n ce characteristics uw duty cycle (%) 0 switch peak current (a) 2.5 2.0 1.5 1.0 0.5 0 80 1375/76 g08 20 40 60 100 typical guaranteed minimum switch peak current limit junction temperature ( c) ?0 2.44 2.43 2.42 2.41 2.40 100 1375/76 g09 25 0 25 50 75 125 feedback voltage (v) current ( a) 2.0 1.5 1.0 0.5 0 voltage current feedback pin voltage and current
5 lt1375/lt1376 13756fd typical perfor m a n ce characteristics uw temperature ( c) ?0 500 400 300 200 8 4 0 25 75 1375/76 g04 ?5 0 50 100 125 current ( a) current required to force shutdown (flows out of pin). after shutdown, current drops to a few a at 2.38v standby threshold (current flows out of pin) shutdown pin bias current junction temperature ( c) ?0 transconductance ( mho) 2500 2000 1500 1000 500 0 0 50 75 1375/76 g02 ?5 25 100 125 error amplifier transconductance frequency (hz) gain ( mho) phase (deg) 3000 2500 2000 1500 1000 500 200 150 100 50 0 ?0 100 10k 100k 10m 1375/76 g03 1k 1m gain phase error amplifier equivalent circuit r out 200k c out 12pf v c r load = 50 ? v fb 2 10 ? ) ( error amplifier transconductance frequency foldback load current (ma) 0 input voltage (v) 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 10 100 1000 1375/76 g12 minimum input voltage can be reduced by adding a small external pnp. see applications information minimum voltage to start with standard circuit minimum voltage to run with standard circuit lt1376 minimum input voltage with 5v output shutdown supply current input voltage (v) 0 input supply current ( a) 30 25 20 15 10 5 0 5101520 1375/76 g06 25 v shutdown = 0v junction temperature ( c) ?0 2.40 2.36 2.32 0.8 0.4 0 25 75 1375/76 g05 ?5 0 50 100 125 shutdown pin voltage (v) standby start-up shutdown standby and shutdown thresholds shutdown supply current shutdown voltage (v) 0 input supply current ( a) 150 125 100 75 50 25 0 0.1 0.2 0.3 0.4 1375/76 g07 0.5 v in = 25v v in = 10v feedback pin voltage (v) 0 switching frequency (khz) or current ( a) 500 400 300 200 100 0 2.0 1375/76 g10 0.5 1.0 1.5 2.5 switching frequency feedback pin current switching frequency junction temperature ( c) ?0 600 550 500 450 400 100 1375/76 g11 25 0 25 50 75 125 frequency (khz)
6 lt1375/lt1376 13756fd typical perfor m a n ce characteristics u w input voltage (v) 0 current (a) 1.50 1.25 1.00 0.75 0.50 0.25 0 5101520 1375/76 g13 25 l = 20 h l = 10 h l = 5 h v out = 10v input voltage (v) 0 current (a) 1.50 1.25 1.00 0.75 0.50 0.25 0 5101520 1375/76 g14 25 l = 20 h l = 10 h l = 5 h v out = 3.3v maximum load current at v out = 10v maximum load current at v out = 3.3v maximum load current at v out = 5v input voltage (v) 0 current (a) 1.50 1.25 1.00 0.75 0.50 0.25 0 5101520 1375/76 g15 25 l = 20 h l = 10 h l = 5 h v out = 5v pi n fu n ctio n s uuu boost: the boost pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar npn power switch. without this added voltage, the typical switch voltage loss would be about 1.5v. the additional boost voltage allows the switch to saturate and voltage loss approximates that of a 0.3 ? fet structure, but with much smaller die area. efficiency improves from 75% for conventional bipolar designs to > 87% for these new parts. v sw : the switch pin is the emitter of the on-chip power npn switch. it is driven up to the input pin voltage during switch on time. inductor current drives the switch pin negative during switch off time. negative voltage is clamped with the external catch diode. maximum negative switch voltage allowed is 0.8v. shdn: the shutdown pin is used to turn off the regulator and to reduce input drain current to a few microamperes. actually, this pin has two separate thresholds, one at 2.38v to disable switching, and a second at 0.4v to force complete micropower shutdown. the 2.38v threshold functions as an accurate undervoltage lockout (uvlo). this is sometimes used to prevent the regulator from operating until the input voltage has reached a predeter- mined level. switch current (a) 0 boost pin current (ma) 12 10 8 6 4 2 0 0.25 0.50 0.75 1.00 1375/76 g16 1.25 t j = 25 c boost pin current v c pin shutdown threshold switch current (a) 0 switch voltage (v) 0.8 0.6 0.4 0.2 0 0.25 0.50 0.75 1.00 1375/76 g18 1.25 1.50 t j = 25 c switch voltage drop junction temperature ( c) ?0 1.4 1.2 1.0 0.8 0.6 0.4 100 1375/76 g11 25 0 25 50 75 125 threshold voltage (v) shutdown
7 lt1375/lt1376 13756fd pi n fu n ctio n s uuu v in : this is the collector of the on-chip power npn switch. this pin powers the internal circuitry and internal regulator when the bias pin is not present. at npn switch on and off, high dl/dt edges occur on this pin. keep the external bypass and catch diode close to this pin. all trace induc- tance on this path will create a voltage spike at switch off, adding to the v ce voltage across the internal npn. bias (lt1376 only): the bias pin is used to improve efficiency when operating at higher input voltages and light load current. connecting this pin to the regulated output voltage forces most of the internal circuitry to draw its operating current from the output voltage rather than the input supply. this is a much more efficient way of doing business if the input voltage is much higher than the output. minimum output voltage setting for this mode of operation is 3.3v . efficiency improvement at v in = 20v, v out = 5v, and i out = 25ma is over 10%. sync (lt1375 only): the sync pin is used to synchro- nize the internal oscillator to an external signal. it is directly logic compatible and can be driven with any signal be- tween 10% and 90% duty cycle. the synchronizing range is equal to initial operating frequency, up to 900khz. see synchronizing section in applications information for details. fb/sense: the feedback pin is used to set output voltage, using an external voltage divider that generates 2.42v at the pin with the desired output voltage. the fixed voltage (-5) parts have the divider included on the chip, and the fb pin is used as a sense pin, connected directly to the 5v output. two additional functions are performed by the fb pin. when the pin voltage drops below 1.7v, switch current limit is reduced. below 1v, switching frequency is also reduced. see feedback pin function section in appli- cations information for details. v c : the v c pin is the output of the error amplifier and the input of the peak switch current comparator. it is normally used for frequency compensation, but can do double duty as a current clamp or control loop override. this pin sits at about 1v for very light loads and 2v at maximum load. it can be driven to ground to shut off the regulator, but if driven high, current must be limited to 4ma. gnd: the gnd pin connection needs consideration for two reasons. first, it acts as the reference for the regulated output, so load regulation will suffer if the ?round?end of the load is not at the same voltage as the gnd pin of the ic. this condition will occur when load current or other currents flow through metal paths between the gnd pin and the load ground point. keep the ground path short between the gnd pin and the load, and use a ground plane when possible. the second consideration is emi caused by gnd pin current spikes. internal capacitance between the v sw pin and the gnd pin creates very narrow (<10ns) current spikes in the gnd pin. if the gnd pin is connected to system ground with a long metal trace, this trace may radiate excess emi. keep the path between the input bypass and the gnd pin short. block diagra m w the lt1376 is a constant frequency, current mode buck converter. this means that there is an internal clock and two feedback loops that control the duty cycle of the power switch. in addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. a switch cycle starts with an oscilla- tor pulse which sets the r s flip-flop to turn the switch on. when switch current reaches a level set by the inverting input of the comparator, the flip-flop is reset and the switch turns off. output voltage control is obtained by using the output of the error amplifier to set the switch current trip point. this technique means that the error amplifier commands current to be delivered to the output rather than voltage. a voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180 shift will occur. the current fed system will have 90 phase shift at a much lower frequency, but will not have the additional 90 shift until well beyond the lc resonant frequency. this makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. most of the circuitry of the lt1376 operates from an internal 2.9v bias line. the bias regulator normally draws power from the regulator input pin, but if the bias pin is
8 lt1375/lt1376 13756fd connected to an external voltage higher than 3v, bias power will be drawn from the external source (typically the regulated output voltage). this will improve efficiency if the bias pin voltage is lower than regulator input voltage. high switch efficiency is attained by using the boost pin to provide a voltage to the switch driver which is higher block diagra m w than the input voltage, allowing switch to be saturated. this boosted voltage is generated with an external capaci- tor and diode. two comparators are connected to the shutdown pin. one has a 2.38v threshold for undervoltage lockout and the second has a 0.4v threshold for complete shutdown. + + + + input 2.9v bias regulator 500khz oscillator frequency shift circuit v sw fb v c gnd 1375/76 bd slope comp 0.05 ? bias internal v cc current sense amplifier voltage gain = 10 sync shutdown comparator current comparator error amplifier g m = 2000 mho foldback current limit clamp boost r s flip-flop driver circuitry s r 0.9v lockout comparator 0.37v 3.5 a q2 q1 power switch 2.38v 2.42v + shdn figure 1. block diagram applicatio n s i n for m atio n wu u u feedback pin functions the feedback (fb) pin on the lt1376 is used to set output voltage and also to provide several overload protection features. the first part of this section deals with selecting resistors to set output voltage and the remaining part talks about foldback frequency and current limiting created by the fb pin. please read both parts before committing to a final design. the fixed 5v lt1376-5 has internal divider resistors and the fb pin is renamed sense, connected directly to the output. the suggested value for the output divider resistor (see figure 2) from fb to ground (r2) is 5k or less, and a formula for r1 is shown below. the output voltage error caused by ignoring the input bias current on the fb pin is less than 0.25% with r2 = 5k. a table of standard 1% values is shown in table 1 for common output voltages.
9 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u + 2.4v v sw v c gnd 1375/76 f02 to frequency shifting r3 1k r4 1k r1 r2 5k output 5v r5 5k error amplifier fb 1.6v q1 lt1375/lt1376 q2 + figure 2. frequency and current limit foldback please read the following if divider resistors are increased above the suggested values. r rv out 1 2242 242 = ? () . . table 1 output r1 % error at output voltage r2 (nearest 1%) due to discreet 1% (v) (k ? )(k ? ) resistor steps 3 4.99 1.21 + 0.23 3.3 4.99 1.82 + 0.08 5 4.99 5.36 + 0.39 6 4.99 7.32 0.5 8 4.99 11.5 0.04 10 4.99 15.8 + 0.83 12 4.99 19.6 0.62 15 4.99 26.1 + 0.52 more than just voltage feedback the feedback (fb) pin is used for more than just output voltage sensing. it also reduces switching frequency and current limit when output voltage is very low (see the frequency foldback graph in typical performance char- acteristics). this is done to control power dissipation in both the ic and in the external diode and inductor during short-circuit conditions. a shorted output requires the switching regulator to operate at very low duty cycles, and the average current through the diode and inductor is equal to the short-circuit current limit of the switch (typi- cally 2a for the lt1376, folding back to less than 1a). minimum switch on time limitations would prevent the switcher from attaining a sufficiently low duty cycle if switching frequency were maintained at 500khz, so fre- quency is reduced by about 5:1 when the feedback pin voltage drops below 1v (see frequency foldback graph). this does not affect operation with normal load condi- tions; one simply sees a gear shift in switching frequency during start-up as the output voltage rises. in addition to lower switching frequency, the lt1376 also operates at lower switch current limit when the feedback pin voltage drops below 1.7v. q2 in figure 2 performs this function by clamping the v c pin to a voltage less than its normal 2.3v upper clamp level. this foldback current limit greatly reduces power dissipation in the ic, diode and inductor during short-circuit conditions. again, it is nearly transparent to the user under normal load conditions. the only loads which may be affected are current source loads which maintain full load current with output voltage less than 50% of final value. in these rare situations the feedback pin can be clamped above 1.5v with an external diode to defeat foldback current limit. caution: clamping the feedback pin means that frequency shifting will also be defeated, so a combination of high input voltage and dead shorted output may cause the lt1376 to lose control of current limit. the internal circuitry which forces reduced switching frequency also causes current to flow out of the feedback
10 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u pin when output voltage is low. the equivalent circuitry is shown in figure 2. q1 is completely off during normal operation. if the fb pin falls below 1v, q1 begins to conduct current and reduces frequency at the rate of approximately 5khz/ a. to ensure adequate frequency foldback (under worst-case short-circuit conditions), the external divider thevinin resistance must be low enough to pull 150 a out of the fb pin with 0.6v on the pin (r div 4k). the net result is that reductions in frequency and current limit are affected by output voltage divider imped- ance. although divider impedance is not critical, caution should be used if resistors are increased beyond the suggested values and short-circuit conditions will occur with high input voltage . high frequency pickup will in- crease and the protection accorded by frequency and current foldback will decrease. maximum output load current maximum load current for a buck converter is limited by the maximum switch current rating (i p ) of the lt1376. this current rating is 1.5a up to 50% duty cycle (dc), decreasing to 1.35a at 80% duty cycle. this is shown graphically in typical performance characteristics and as shown in the formula below: i p = 1.5a for dc 50% i p = 1.65a ?0.15 (dc) ?0.26 (dc) 2 for 50% < dc < 90% dc = duty cycle = v out /v in example: with v out = 5v, v in = 8v; dc = 5/8 = 0.625, and; i sw(max) = 1.64 ?0.15 (0.625) ?0.26 (0.625) 2 = 1.44a current rating decreases with duty cycle because the lt1376 has internal slope compensation to prevent cur- rent mode subharmonic switching. for more details, read application note 19. the lt1376 is a little unusual in this regard because it has nonlinear slope compensation which gives better compensation with less reduction in current limit. maximum load current would be equal to maximum switch current for an infinitely large inductor , but with finite inductor size, maximum load current is reduced by one-half peak-to-peak inductor current. the following formula assumes continuous mode operation, implying that the term on the right is less than one-half of i p . i out(max) = continuous mode for the conditions above and l = 10 h, i a out max ( ) ? = ? () ? () ? ? ? ? ? ? ? ? () = ? = 144 58 5 2 10 500 10 8 144 019 125 53 . ... at v in = 15v, duty cycle is 33%, so i p is just equal to a fixed 1.5a, and i out(max) is equal to: 15 515 5 2 10 500 10 15 15 033 117 53 . .. . ? () ? () ? ? ? ? ? ? ? ? () = ? = ? a note that there is less load current available at the higher input voltage because inductor ripple current increases. this is not always the case. certain combinations of inductor value and input voltage range may yield lower available load current at the lowest input voltage due to reduced peak switch current at high duty cycles. if load current is close to the maximum available, please check maximum available current at both input voltage ex- tremes. to calculate actual peak switch current with a given set of conditions, use: ii vvv lfv sw peak out out in out in ( ) =+ ? () ()()( ) 2 for lighter loads where discontinuous operation can be used, maximum load current is equal to: i out(max) = discontinuous mode i p ? () ? () ()()( ) vvv lfv out in out in 2 iflv vvv p out out in out ()()()( ) () ? () 2 2
11 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u must withstand continuous fault conditions. if maxi- mum load current is 0.5a, for instance, a 0.5a inductor may not survive a continuous 1.5a overload condition. dead shorts will actually be more gentle on the induc- tor because the lt1376 has foldback current limiting. 2. calculate peak inductor current at full load current to ensure that the inductor will not saturate. peak current can be significantly higher than output current, espe- cially with smaller inductors and lighter loads, so don? omit this step. powdered iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. other core materials fall in between somewhere. the following formula assumes continu- ous mode of operation, but it errs only slightly on the high side for discontinuous mode, so it can be used for all conditions. ii vvv flv peak out out in out in =+ ? () ()( )( ) 2 v in = maximum input voltage f = switching frequency, 500khz 3. decide if the design can tolerate an ?pen?core geom- etry like a rod or barrel, which have high magnetic field radiation, or whether it needs a closed core like a toroid to prevent emi problems. one would not want an open core next to a magnetic storage media, for instance! this is a tough decision because the rods or barrels are temptingly cheap and small and there are no helpful guidelines to calculate when the magnetic field radia- tion will be a problem. 4. start shopping for an inductor (see representative surface mount units in table 2) which meets the re- quirements of core shape, peak current (to avoid satu- ration), average current (to limit heating), and fault current (if the inductor gets too hot, wire insulation will melt and cause turn-to-turn shorts). keep in mind that all good things like high efficiency, low profile, and high temperature operation will increase cost, sometimes dramatically. get a quote on the cheapest unit first to calibrate yourself on price, then ask for what you really want. example: with l = 2 h, v out = 5v, and v in(max ) = 15v, ima out max ( ) ? = () ? ? ? ? ? ? ? ? () () ? () = 1 5 500 10 2 10 15 2 5 15 5 338 2 36 . the main reason for using such a tiny inductor is that it is physically very small, but keep in mind that peak-to-peak inductor current will be very high. this will increase output ripple voltage. if the output capacitor has to be made larger to reduce ripple voltage, the overall circuit could actually wind up larger. choosing the inductor and output capacitor for most applications the output inductor will fall in the range of 3 h to 20 h. lower values are chosen to reduce physical size of the inductor. higher values allow more output current because they reduce peak current seen by the lt1376 switch, which has a 1.5a limit. higher values also reduce output ripple voltage, and reduce core loss. graphs in the typical performance characteristics section show maximum output load current versus inductor size and input voltage. a second graph shows core loss versus inductor size for various core materials. when choosing an inductor you might have to consider maximum load current, core and copper losses, allowable component height, output voltage ripple, emi, fault cur- rent in the inductor, saturation, and of course, cost. the following procedure is suggested as a way of handling these somewhat complicated and conflicting requirements. 1. choose a value in microhenries from the graphs of maximum load current and core loss. choosing a small inductor with lighter loads may result in discontinuous mode of operation, but the lt1376 is designed to work well in either mode. keep in mind that lower core loss means higher cost, at least for closed core geometries like toroids. the core loss graphs show both absolute loss and percent loss for a 5w output, so actual percent losses must be calculated for each situation. assume that the average inductor current is equal to load current and decide whether or not the inductor
12 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u 5. after making an initial choice, consider the secondary things like output voltage ripple, second sourcing, etc. use the experts in the linear technology? applica- tions department if you feel uncertain about the final choice. they have experience with a wide range of inductor types and can tell you about the latest devel- opments in low profile, surface mounting, etc. table 2 series core vendor/ value dc core resis- mater- height part no. ( h) (amps) type tance( ? ) ial (mm) coiltronics ctx5-1 5 2.3 tor 0.027 km 4.2 ctx10-1 10 1.9 tor 0.039 km 4.2 ctx20-1 20 1.0 tor 0.137 km 4.2 ctx15-2 15 1.8 tor 0.058 km 6.0 ctx20-3 20 1.5 tor 0.093 km 4.7 ctx20-4 20 2.2 tor 0.059 km 6.4 ctx5-1p 5 1.8 tor 0.021 52 4.2 ctx10-1p 10 1.6 tor 0.030 52 4.2 ctx15-1p 15 1.2 tor 0.046 52 4.2 ctx20-1p 20 1.0 tor 0.081 52 4.2 ctx20-2p 20 1.3 tor 0.052 52 6.0 ctx20-4p 20 1.8 tor 0.039 52 6.35 sumida cdrh64 10 1.7 sc 0.084 fer 4.5 cdrh74 22 1.2 sc 0.077 fer 4.5 cdrh73 10 1.7 sc 0.055 fer 3.4 cdrh73 22 1.1 sc 0.15 fer 3.4 cd73 10 1.4 open 0.062 fer 3.5 cd73 18 1.1 open 0.085 fer 3.5 cd104 10 2.4 open 0.041 fer 4.0 cd104 18 1.7 open 0.062 fer 4.0 gowanda sm20-102k 10 1.3 open 0.038 fer 7.0 sm20-152k 15 1.3 open 0.049 fer 7.0 sm20-222k 22 1.3 open 0.059 fer 7.0 dale ihsm-4825 10 3.1 open 0.071 fer 5.6 ihsm-4825 22 1.7 open 0.152 fer 5.6 ihsm-5832 10 4.3 open 0.053 fer 7.1 ihsm-5832 22 2.8 open 0.12 fer 7.1 ihsm-7832 22 3.8 open 0.054 fer 7.1 tor = toroid sc = semi-closed geometry fer = ferrite core material 52 = type 52 powdered iron core material km = kool m output capacitor the output capacitor is normally chosen by its effective series resistance (esr), because this is what determines output ripple voltage. at 500khz, any polarized capacitor is essentially resistive. to get low esr takes volume , so physically smaller capacitors have high esr. the esr range for typical lt1376 applications is 0.05 ? to 0.5 ? . a typical output capacitor is an avx type tps, 100 f at 10v, with a guaranteed esr less than 0.1 ? . this is a ??size surface mount solid tantalum capacitor. tps capacitors are specially constructed and tested for low esr, so they give the lowest esr for a given volume. the value in microfarads is not particularly critical, and values from 22 f to greater than 500 f work well, but you cannot cheat mother nature on esr. if you find a tiny 22 f solid tantalum capacitor, it will have high esr, and output ripple voltage will be terrible. table 3 shows some typical solid tantalum surface mount capacitors. table 3. surface mount solid tantalum capacitor esr and ripple current e case size esr (max., ? ) ripple current (a) avx tps, sprague 593d 0.1 to 0.3 0.7 to 1.1 avx taj 0.7 to 0.9 0.4 d case size avx tps, sprague 593d 0.1 to 0.3 0.7 to 1.1 avx taj 0.9 to 2.0 0.36 to 0.24 c case size avx tps 0.2 (typ) 0.5 (typ) avx taj 1.8 to 3.0 0.22 to 0.17 b case size avx taj 2.5 to 10 0.16 to 0.08 many engineers have heard that solid tantalum capacitors are prone to failure if they undergo high surge currents. this is historically true, and type tps capacitors are specially tested for surge capability, but surge ruggedness is not a critical issue with the output capacitor. solid tantalum capacitors fail during very high turn-on surges, which do not occur at the output of regulators. high
13 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u discharge surges, such as when the regulator output is dead shorted, do not harm the capacitors. unlike the input capacitor, rms ripple current in the output capacitor is normally low enough that ripple cur- rent rating is not an issue. the current waveform is triangular with a typical value of 200ma rms . the formula to calculate this is: output capacitor ripple current (rms): i vvv lfv ripple rms out in out in ( ) = () ? () ()()( ) 029 . ceramic capacitors higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. these are tempt- ing for switching regulator use because of their very low esr. unfortunately, the esr is so low that it can cause loop stability problems. solid tantalum capacitor? esr generates a loop ?ero?at 5khz to 50khz that is instrumen- tal in giving acceptable loop phase margin. ceramic ca- pacitors remain capacitive to beyond 300khz and usually resonate with their esl before esr becomes effective. they are appropriate for input bypassing because of their high ripple current ratings and tolerance of turn-on surges. for further information on ceramic and other capacitor types please refer to design note 95. output ripple voltage figure 3 shows a typical output ripple voltage waveform for the lt1376. ripple voltage is determined by the high frequency impedance of the output capacitor, and ripple current through the inductor. peak-to-peak ripple current through the inductor into the output capacitor is: i vvv vlf p out in out in -p = () ? () ()()() for high frequency switchers, the sum of ripple current slew rates may also be relevant and can be calculated from: di dt v l in = peak-to-peak output ripple voltage is the sum of a triwave created by peak-to-peak ripple current times esr, and a square wave created by parasitic inductance (esl) and ripple current slew rate. capacitive reactance is assumed to be small compared to esr or esl. v i esr esl di dt ripple = ()( ) + () p-p example: with v in =10v, v out = 5v, l = 10 h, esr = 0.1 ? , esl = 10nh: ia di dt va mv ripple p-p p-p = () ? () () ? ? ? ? ? ? ? ? = == = ()() + ? ? ? ? ? ? ? ? =+= ? ? ? 510 5 10 10 10 500 10 05 10 10 10 10 05 01 10 10 10 0 05 0 01 60 63 6 6 96 . .. .. v out at i out = 1a v out at i out = 50ma inductor current at i out = 1a 0.5 s/div 1375/76 f03 figure 3. lt1376 ripple voltage waveform inductor current at i out = 50ma 20mv/div 0.5a/div catch diode the suggested catch diode (d1) is a 1n5818 schottky, or its motorola equivalent, mbr130. it is rated at 1a average forward current and 30v reverse voltage. typical forward voltage is 0.42v at 1a. the diode conducts current only during switch off time. peak reverse voltage is equal to
14 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u regulator input voltage. average forward current in normal operation can be calculated from: i ivv v d avg out in out in ( ) = ? () this formula will not yield values higher than 1a with maximum load current of 1.25a unless the ratio of input to output voltage exceeds 5:1. the only reason to consider a larger diode is the worst-case condition of a high input voltage and overloaded (not shorted) output. under short- circuit conditions, foldback current limit will reduce diode current to less than 1a, but if the output is overloaded and does not fall to less than 1/3 of nominal output voltage, foldback will not take effect. with the overloaded condi- tion, output current will increase to a typical value of 1.8a, determined by peak switch current limit of 2a. with v in = 15v, v out = 4v (5v overloaded) and i out = 1.8a: ia d avg ( ) = ? () = 1 8 15 4 15 132 . . this is safe for short periods of time, but it would be prudent to check with the diode manufacturer if continu- ous operation under these conditions must be tolerated. boost pin considerations for most applications, the boost components are a 0.1 f capacitor and a 1n914 or 1n4148 diode. the anode is connected to the regulated output voltage and this gener- ates a voltage across the boost capacitor nearly identical to the regulated output. in certain applications, the anode may instead be connected to the unregulated input volt- age. this could be necessary if the regulated output voltage is very low (< 3v) or if the input voltage is less than 6v. efficiency is not affected by the capacitor value, but the capacitor should have an esr of less than 2 ? to ensure that it can be recharged fully under the worst-case condi- tion of minimum input voltage. almost any type of film or ceramic capacitor will work fine. warning! peak voltage on the boost pin is the sum of unregulated input voltage plus the voltage across the boost capacitor. this normally means that peak boost pin voltage is equal to input voltage plus output voltage, but when the boost diode is connected to the regulator input, peak boost pin voltage is equal to twice the input voltage. be sure that boost pin voltage does not exceed its maximum rating . for nearly all applications, a 0.1uf boost capacitor works just fine, but for the curious, more details are provided here. the size of the boost capacitor is determined by switch drive current requirements. during switch on time, drain current on the capacitor is approximately 10ma + i out / 75. at peak load current of 1.25a, this gives a total drain of 27ma. capacitor ripple voltage is equal to the product of on time and drain current divided by capacitor value; ? v = t on ?27ma/c. to keep capacitor ripple voltage to less than 0.5v (a slightly arbitrary number) at the worst- case condition of t on = 1.8 s, the capacitor needs to be 0.1 f. boost capacitor ripple voltage is not a critical parameter, but if the minimum voltage across the capaci- tor drops to less than 3v, the power switch may not saturate fully and efficiency will drop. an approximate formula for absolute minimum capacitor value is: c ma i v v fv v min out out in out = + ()() () ? () 10 75 3 // f = switching frequency v out = regulated output voltage v in = minimum input voltage this formula can yield capacitor values substantially less than 0.1 f, but it should be used with caution since it does not take into account secondary factors such as capacitor series resistance, capacitance shift with temperature and output overload. shutdown function and undervoltage lockout figure 4 shows how to add undervoltage lockout (uvlo) to the lt1376. typically, uvlo is used in situations where the input supply is current limited , or has a relatively high source resistance. a switching regulator draws constant power from the source, so source current increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current limit
15 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u + + 2.38v 0.37v gnd v sw lt1375/lt1376 input r fb r hi 1375/76 f04 output shdn standby in total shutdown 3.5 a r lo c1 + figure 4. undervoltage lockout or latch low under low source voltage conditions. uvlo prevents the regulator from operating at source voltages where these problems might occur. threshold voltage for lockout is about 2.38v, slightly less than the internal 2.42v reference voltage. a 3.5 a bias current flows out of the pin at threshold. this internally generated current is used to force a default high state on the shutdown pin if the pin is left open. when low shut- down current is not an issue, the error due to this current can be minimized by making r lo 10k or less. if shutdown current is an issue, r lo can be raised to 100k, but the error due to initial bias current and changes with temperature should be considered. rk r rv v vr a lo hi lo in lo = () = ? () ? () 10 238 238 35 to 100k 25k suggested . .. v in = minimum input voltage keep the connections from the resistors to the shutdown pin short and make sure that interplane or surface capaci- tance to the switching nodes are minimized. if high resis- tor values are used, the shutdown pin should be bypassed with a 1000pf capacitor to prevent coupling problems from the switch node. if hysteresis is desired in the undervoltage lockout point, a resistor r fb can be added to the output node. resistor values can be calculated from: r rv vv v ra rrv v hi lo in out fb hi out = ? + () + [] ? () = ()( ) 238 1 238 235 ./ .. / ?? ? 25k suggested for r lo v in = input voltage at which switching stops as input voltage descends to trip level ? v = hysteresis in input voltage level example: output voltage is 5v, switching is to stop if input voltage drops below 12v and should not restart unless input rises back to 13.5v. ? v is therefore 1.5v and v in = 12v. let r lo = 25k. r k ka k k rk k hi fb = ? + () + [] ? () = () = = () = 25 12 2 38 1 5 5 1 1 5 238 25 35 25 10 41 229 114 114 5 1 5 380 ../ . .. . . /. switch node considerations for maximum efficiency, switch rise and fall times are made as short as possible. to prevent radiation and high frequency resonance problems, proper layout of the com- ponents connected to the switch node is essential. b field
16 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u (magnetic) radiation is minimized by keeping catch diode, switch pin, and input bypass capacitor leads as short as possible. e field radiation is kept low by minimizing the length and area of all traces connected to the switch pin and boost pin. a ground plane should always be used under the switcher circuitry to prevent interplane cou- pling. a suggested layout for the critical components is shown in figure 5. note that the feedback resistors and compensation components are kept as far as possible from the switch node. also note that the high current ground path of the catch diode and input capacitor are kept very short and separate from the analog ground line. the high speed switching current path is shown schemati- cally in figure 6. minimum lead length in this path is essential to ensure clean switching and low emi. the path including the switch, catch diode, and input capacitor is the only one containing nanosecond rise and fall times. if you follow this path on the pc layout, you will see that it is irreducibly short. if you move the diode or input capacitor away from the lt1376, get your resum? in order. the other paths contain only some combination of dc and 500khz triwave, so are much less critical. figure 5. suggested layout input c2 c3 d2 c c r c r1 c1 1375/76 f05 d1 l1 r2 boost in sw bias v c fb gnd shdn shutdown output minimize area of connections to the switch node and boost node keep input capacitor and catch diode close to regulator and terminate them to same point connect output capacitor directly to heavy ground take output directly from end of output capacitor to avoid parasitic resistance and inductance (kelvin connection) minimize size of feedback pin connections to avoid pickup terminate feedback resistors and compensation components directly to switcher ground pin ground ring need not be as shown. (normally exists as internal plane) figure 6. high speed switching path 1375/76 f06 5v l1 v in high frequency circulating path load switch node
17 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u parasitic resonance resonance or ?inging?may sometimes be seen on the switch node (see figure 7). very high frequency ringing following switch rise time is caused by switch/diode/input capacitor lead inductance and diode capacitance. schot- tky diodes have very high ??junction capacitance that can ring for many cycles when excited at high frequency. if total lead length for the input capacitor, diode and switch path is 1 inch, the inductance will be approximately 25nh. schottky diode capacitance of 100pf will create a reso- nance at 100mhz. this ringing is not harmful to the lt1376 and can normally be ignored. overshoot or ringing following switch fall time is created by switch capacitance rather than diode capacitance. this ringing per se is not harmful, but the overshoot can cause problems if the amplitude becomes too high. the negative voltage can forward bias parasitic junctions on the ic chip and cause erratic switching. the lt1376 has special circuitry inside which mitigates this problem, but negative voltages over 1v lasting longer than 10ns should be avoided. note that 100mhz oscilloscopes are barely fast enough to see the details of the falling edge overshoot in figure 7. a second, much lower frequency ringing is seen during switch off time if load current is low enough to allow the inductor current to fall to zero during part of the switch off time (see figure 8). switch and diode capacitance reso- nate with the inductor to form damped ringing at 1mhz to 10 mhz. again, this ringing is not harmful to the regulator and it has not been shown to contribute significantly to emi. any attempt to damp it with a resistive snubber will degrade efficiency. input bypassing and voltage range input bypass capacitor step-down converters draw current from the input supply in pulses. the average height of these pulses is equal to load current, and the duty cycle is equal to v out /v in . rise and fall time of the current is very fast. a local bypass capacitor across the input supply is necessary to ensure proper operation of the regulator and minimize the ripple current fed back into the input supply. the capacitor also forces switching current to flow in a tight local loop, minimizing emi . do not cheat on the ripple current rating of the input bypass capacitor, but also don? get hung up on the value in microfarads . the input capacitor is intended to absorb all the switching current ripple, which can have an rms value as high as one half of load current. ripple current ratings on the capacitor must be observed to ensure reliable operation. the actual value of the capacitor in microfarads is not particularly important because at 500khz, any value above 5 f is essentially resistive. rms ripple current rating is the critical parameter. actual rms current can be calculated from: iivvvv ripple rms out out in out in ( ) = ? () / 2 the term inside the radical has a maximum value of 0.5 when input voltage is twice output, and stays near 0.5 for a relatively wide range of input voltages. it is common 5v/div figure 7. switch node resonance 20ns/div 1375/76 f07 20ns/div 1375/76 f11 0.5 s/div 1375/76 f08 figure 8. discontinuous mode ringing 5v/div 100ma/div rise and fall waveforms are superimposed (pulse width is not 120ns) switch node voltage inductor current
18 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u practice therefore to simply use the worst-case value and assume that rms ripple current is one half of load current. at maximum output current of 1.5a for the lt1376, the input bypass capacitor should be rated at 0.75a ripple current. note however, that there are many secondary considerations in choosing the final ripple current rating. these include ambient temperature, average versus peak load current, equipment operating schedule, and required product lifetime. for more details, see application notes 19 and 46, and design note 95. input capacitor type some caution must be used when selecting the type of capacitor used at the input to regulators. aluminum electrolytics are lowest cost, but are physically large to achieve adequate ripple current rating, and size con- straints (especially height), may preclude their use. ce- ramic capacitors are now available in larger values, and their high ripple current and voltage rating make them ideal for input bypassing. cost is fairly high and footprint may also be somewhat large. solid tantalum capacitors would be a good choice, except that they have a history of occasional spectacular failures when they are subjected to large current surges during power-up. the capacitors can short and then burn with a brilliant white light and lots of nasty smoke. this phenomenon occurs in only a small percentage of units, but it has led some oem companies to forbid their use in high surge applications. the input bypass capacitor of regulators can see these high surges when a battery or high capacitance source is connected. several manufacturers have developed a line of solid tantalum capacitors specially tested for surge capability (avx tps series for instance, see table 3), but even these units may fail if the input voltage surge approaches the maximum voltage rating of the capacitor. avx recom- mends derating capacitor voltage by 2:1 for high surge applications. the highest voltage rating is 50v, so 25v may be a practical upper limit when using solid tantalum capacitors for input bypassing. larger capacitors may be necessary when the input volt- age is very close to the minimum specified on the data sheet. small voltage dips during switch on time are not normally a problem, but at very low input voltage they may cause erratic operation because the input voltage drops below the minimum specification. problems can also occur if the input-to-output voltage differential is near minimum. the amplitude of these dips is normally a function of capacitor esr and esl because the capacitive reactance is small compared to these terms. esr tends to be the dominate term and is inversely related to physical capacitor size within a given capacitor type. minimum input voltage (after start-up) minimum input voltage to make the lt1376 ?un?cor- rectly is typically 5v, but to regulate the output, a buck converter input voltage must always be higher than the output voltage. to calculate minimum operating input voltage, switch voltage loss and maximum duty cycle must be taken into account. with the lt1376, there is the additional consideration of proper operation of the boost circuit. the boost circuit allows the power switch to saturate for high efficiency, but it also sometimes results in a start-up or operating voltage that is several volts higher than the standard running voltage, especially at light loads. an approximate formula to calculate minimum running voltage at load currents above 100ma is: v vi in min out out ( ) = + ()( ) 04 088 . . ? minimum start-up voltage and operation at light loads the boost capacitor supplies current to the boost pin during switch on time. this capacitor is recharged only during switch off time. under certain conditions of light load and low input voltage, the capacitor may not be recharged fully during the relatively short off time. this causes the boost voltage to collapse and minimum input voltage is increased. start-up voltage at light loads is higher than normal running voltage for the same reasons. the graph in figure 9 shows minimum input voltage for a 5v output, both for start-up and for normal operation. the circuit in figure 10 will allow operation at light load with low input voltages. it uses a small pnp to charge the boost capacitor c2, and an extra diode d3 to complete the power path from v sw to the boost capacitor.
19 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u load current (a) 0.001 input voltage (v) 8.0 7.5 7.0 6.5 6.0 5.5 5.0 0.01 0.1 1 1375/76 f09 (a) (c) (d) (a) minimum voltage to start with standard circuit (b) minimum voltage to run with standard circuit (c) minimum voltage to start with pnp (d) minimum voltage to run with pnp (b) figure 9. minimum input voltage figure 10. reducing minimum input voltage output input 1375/76 f10 c2 0.1 f c c d3 1n914 q1 2n3905 c1 d1 1n914 l1 boost lt1376-5 v in v sw sense gnd v c + + compensation section for a discussion of an entirely different cause of subharmonic switching before assum- ing that the cause is insufficient slope compensation. application note 19 has more details on the theory of slope compensation. there is a sync-supply sequence issue with the lt1375. if power is supplied to the regulator after the external sync signal is supplied, the regulator may not start. this is caused by the internal frequency foldback condition that occurs when the fb pin is below 1v (see block diagram description in the data sheet). the oscillator tries to run at 100khz when the fb pin is below 1v, and a high frequency sync signal will then create an extremely low amplitude oscillator waveform. this amplitude may be so low that the switch logic is not triggered to create switching. under the normal regulated condition, the oscillator runs at much higher amplitude with plenty of drive for the switch logic. note that for fixed voltage parts, the fb pin is replaced with a sense pin, and the voltage divider resistors are internal. in that case, the fb pin drops below 1v when the output voltage is less than 40% of its regulated value. there are no sequence problems if the power supply for the sync signal comes from the output of the lt1375. if this is not the case, and the sync signal could be present when power is applied to the regulator, a gate should be used to block sync signals as shown in figure 11. any other technique which prevents sync signals when the regulator output is low will work just as well. it does not matter whether the sync signal is forced high or low; the internal circuitry is edge triggered. synchronizing (available on lt1375 only) the lt1375 has the bias pin replaced with a sync pin, which is used to synchronize the internal oscillator to an external signal. it is directly logic compatible and can be driven with any signal between 10% and 90% duty cycle. the synchronizing range is equal to initial operating fre- quency up to 900khz. this means that minimum practical sync frequency is equal to the worst-case high self- oscillating frequency (560khz), not the typical operating frequency of 500khz. caution should be used when syn- chronizing above 700khz because at higher sync frequen- cies the amplitude of the internal slope compensation used to prevent subharmonic switching is reduced. this type of subharmonic switching only occurs at input volt- ages less than twice output voltage. higher inductor values will tend to eliminate problems. see frequency lt1375 sync v out 1375/76 f11 v in frequency compensation loop frequency compensation of switching regulators can be a rather complicated problem because the reactive components used to achieve high efficiency also figure 11. gating the sync signal
20 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u error amplifier transconductance phase and gain are shown in figure 14. the error amplifier can be modeled as a transconductance of 2000 mho, with an output imped- ance of 200k ? in parallel with 12pf. in all practical applications, the compensation network from v c pin to ground has a much lower impedance than the output impedance of the amplifier at frequencies above 500hz. this means that the error amplifier characteristics them- selves do not contribute excess phase shift to the loop, and the phase/gain characteristics of the error amplifier sec- tion are completely controlled by the external compensa- tion network. in figure 15, full loop phase/gain characteristics are shown with a compensation capacitor of 0.0033 f, giving the error amplifier a pole at 240hz, with phase rolling off to 90 and staying there. the overall loop has a gain of introduce multiple poles into the feedback loop. the inductor and output capacitor on a conventional step- down converter actually form a resonant tank circuit that can exhibit peaking and a rapid 180 phase shift at the resonant frequency. by contrast, the lt1376 uses a ?ur- rent mode?architecture to help alleviate phase shift cre- ated by the inductor. the basic connections are shown in figure 12. figure 13 shows a bode plot of the phase and gain of the power section of the lt1376, measured from the v c pin to the output. gain is set by the 2a/v transcon- ductance of the lt1376 power section and the effective complex impedance from output to ground. gain rolls off smoothly above the 100hz pole frequency set by the 100 f output capacitor. phase drop is limited to about 85 . phase recovers and gain levels off at the zero fre- quency ( 16khz) set by capacitor esr (0.1 ? ). figure 13. response from v c pin to output figure 15. overall loop characteristics frequency (hz) gain: v c pin to output (db) phase: v c pin to output (deg) 40 20 0 ?0 ?0 40 0 ?0 ?0 120 10 1k 10k 1m 1375/76 f13 100 100k gain phase v in = 10v v out = 5v i out = 500ma frequency (hz) loop gain (db) loop phase (deg) 80 60 40 20 0 ?0 200 150 100 50 0 ?0 10 1k 10k 1m 1375/76 f15 100 100k gain phase v in = 10v v out = 5v, i out = 500ma c out = 100 f, 10v, avx tps c c = 3.3nf, r c = 0, l = 10 h figure 12. model for loop response figure 14. error amplifier gain and phase + 2.42v v sw v c lt1375 lt1376 gnd 1375/76 f12 r1 output esr c f c c r c error amplifier fb + r2 c1 current mode power stage g m = 2a/v frequency (hz) gain ( mho) phase (deg) 3000 2500 2000 1500 1000 500 200 150 100 50 0 ?0 100 10k 100k 10m 1375/76 f14 1k 1m gain phase r out 200k c out 12pf v c error amplifier equivalent circuit r load = 50 ? v fb 2 10 ? ) (
21 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u 77db at low frequency, rolling off to unity-gain at 20khz. phase shows a two-pole characteristic until the esr of the output capacitor brings it back above 10khz. phase mar- gin is about 60 at unity-gain. analog experts will note that around 1khz, phase dips very close to the zero phase margin line. this is typical of switch- ing regulators, especially those that operate over a wide range of loads. this region of low phase is not a problem as long as it does not occur near unity-gain. in practice, the variability of output capacitor esr tends to dominate all other effects with respect to loop response. variations in esr will cause unity-gain to move around, but at the same time phase moves with it so that adequate phase margin is maintained over a very wide range of esr ( 3:1). what about a resistor in the compensation network? it is common practice in switching regulator design to add a ?ero?to the error amplifier compensation to increase loop phase margin. this zero is created in the external network in the form of a resistor (r c ) in series with the compensation capacitor. increasing the size of this resis- tor generally creates better and better loop stability, but there are two limitations on its value. first, the combina- tion of output capacitor esr and a large value for r c may cause loop gain to stop rolling off altogether, creating a gain margin problem. an approximate formula for r c where gain margin falls to zero is: r loop v g g esr c out mp ma gain = 1 () = ()()()( ) 242 . g mp = transconductance of power stage = 2a/v g ma = error amplifier transconductance = 2 10 ? esr = output capacitor esr 2.42 = reference voltage with v out = 5v and esr = 0.1 ? , a value of 5.17k for r c would yield zero gain margin, so this represents an upper limit. there is a second limitation however which has nothing to do with theoretical small signal dynamics. this resistor sets high frequency gain of the error amplifier, including the gain at the switching frequency. if switching frequency gain is high enough, output ripple voltage will appear at the v c pin with enough amplitude to muck up proper operation of the regulator. in the marginal case, subharmonic switching occurs, as evidenced by alternat- ing pulse widths seen at the switch node. in more severe cases, the regulator squeals or hisses audibly even though the output voltage is still roughly correct. none of this will show on a theoretical bode plot because bode is an amplitude insensitive analysis. tests have shown that if ripple voltage on the v c is held to less than 100mv p-p , the lt1376 will be well behaved . the formula below will give an estimate of v c ripple voltage when r c is added to the loop, assuming that r c is large compared to the reactance of c c at 500khz. v r g v v esr vlf c ripple c ma in out in ( ) = ()( ) ? ()()() ()()() 24 . g ma = error amplifier transconductance (2000 mho) if a computer simulation of the lt1376 showed that a series compensation resistor of 3k gave best overall loop response, with adequate gain margin, the resulting v c pin ripple voltage with v in = 10v, v out = 5v, esr = 0.1 ? , l = 10 h, would be: v k v c ripple ( ) ? ? = () ? ? ? ? ? ()()() () ? ? ? ? ? ? ? ? = 3 2 10 10 5 0 1 2 4 10 10 10 500 10 0 144 3 63 ?. . this ripple voltage is high enough to possibly create subharmonic switching. in most situations a compromise value (< 2k in this case) for the resistor gives acceptable phase margin and no subharmonic problems. in other cases, the resistor may have to be larger to get acceptable phase response, and some means must be used to control ripple voltage at the v c pin. the suggested way to do this is to add a capacitor (c f ) in parallel with the r c /c c network on the v c pin. pole frequency for this capacitor is typically set at one-fifth of switching frequency so that it provides significant attenuation of switching ripple, but does not add unacceptable phase shift at loop unity-gain frequency. with r c = 3k, c fr k pf f c = ()()() = ? ? ? ? () = 5 2 5 2 500 10 3 531 3
22 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u how do i test loop stability? the ?tandard?compensation for lt1376 is a 3.3nf capacitor for c c , with r c = 0. while this compensation will work for most applications, the ?ptimum?value for loop compensation components depends, to various extent, on parameters which are not well controlled. these include inductor value ( 30% due to production tolerance, load current and ripple current variations), output capacitance ( 20% to 50% due to production tolerance, tempera- ture, aging and changes at the load), output capacitor esr ( 200% due to production tolerance, temperature and aging), and finally, dc input voltage and output load current . this makes it important for the designer to check out the final design to ensure that it is ?obust?and tolerant of all these variations. i check switching regulator loop stability by pulse loading the regulator output while observing transient response at the output, using the circuit shown in figure 16. the regulator loop is ?it?with a small transient ac load current at a relatively low frequency, 50hz to 1khz. this causes the output to jump a few millivolts, then settle back to the original value, as shown in figure 17. a well behaved loop will settle back cleanly, whereas a loop with poor phase or gain margin will ?ing?as it settles. the number of rings indicates the degree of stability, and the frequency of the ringing shows the approximate unity-gain fre- quency of the loop. amplitude of the signal is not particu- larly important, as long as the amplitude is not so high that the loop behaves nonlinearly. the output of the regulator contains both the desired low frequency transient information and a reasonable amount of high frequency (500khz) ripple. the ripple makes it difficult to observe the small transient, so a two-pole, 100khz filter has been added. this filter is not particularly critical; even if it attenuated the transient signal slightly, this wouldn? matter because amplitude is not critical. after verifying that the setup is working correctly, i start varying load current and input voltage to see if i can find any combination that makes the transient response look suspiciously ?ingy.?this procedure may lead to an ad- justment for best loop stability or faster loop transient response. nearly always you will find that loop response looks better if you add in several k ? for r c . do this only if necessary, because as explained before, r c above 1k may require the addition of c f to control v c pin ripple. if everything looks ok, i use a heat gun and cold spray on the circuit (especially the output capacitor) to bring out any temperature-dependent characteristics. figure 16. loop stability test circuit to oscilloscope sync adjustable dc load adjustable input supply 100hz to 1khz 100mv to 1v p-p 100 f to 1000 f ripple filter 1375/76 f16 to x1 oscilloscope probe 3300pf 330pf 50 ? 470 ? 4.7k switching regulator + 0.2ms/div 1375/76 f17 10mv/div v out at i out = 500ma before filter v out at i out = 500ma after filter v out at i out = 50ma after filter load pulse through 50 ? f 780hz 5a/div figure 17. loop stability check
23 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u keep in mind that this procedure does not take initial component tolerance into account. you should see fairly clean response under all load and line conditions to ensure that component variations will not cause problems. one note here: according to murphy, the component most likely to be changed in production is the output capacitor, because that is the component most likely to have manu- facturer variations (in esr) large enough to cause prob- lems. it would be a wise move to lock down the sources of the output capacitor in production. a possible exception to the ?lean response?rule is at very light loads, as evidenced in figure 17 with i load = 50ma. switching regulators tend to have dramatic shifts in loop response at very light loads, mostly because the inductor current becomes discontinuous. one common result is very slow but stable characteristics. a second possibility is low phase margin, as evidenced by ringing at the output with transients. the good news is that the low phase margin at light loads is not particularly sensitive to com- ponent variation, so if it looks reasonable under a transient test, it will probably not be a problem in production. note that frequency of the light load ringing may vary with component tolerance but phase margin generally hangs in there. thermal calculations power dissipation in the lt1376 chip comes from four sources: switch dc loss, switch ac loss, boost circuit current, and input quiescent current. the following formu- las show how to calculate each of these losses. these formulas assume continuous mode operation, so they should not be used for calculating efficiency at light load currents. switch loss: p ri v v ns i v f sw sw out out in out in = ()( ) + ()()() 2 16 boost current loss: p vi v boost out out in = + () 2 0 008 75 ./ quiescent current loss: pv v v v q in out out in = () + () + ? ? ? ? ? ? () 0 001 0 005 0 002 2 .. . r sw = switch resistance ( 0.4) 16ns = equivalent switch current/voltage overlap time f = switch frequency example: with v in = 10v, v out = 5v and i out = 1a: p w pw pw sw boost q = ()()() + ? ? ? ? ()( ) ? ? ? ? =+ = = () + () = = () + () + ()( ) = ? 04 1 5 10 16 10 1 10 500 10 02 008 028 5 0 008 1 75 10 0 053 10 0 001 5 0 005 5 0 002 10 004 2 93 2 2 . .. . ./ . .. . . total power dissipation is 0.28 + 0.053 + 0.04 = 0.37w. thermal resistance for lt1376 package is influenced by the presence of internal or backside planes. with a full plane under the so package, thermal resistance will be about 120 c/w. no plane will increase resistance to about 160 c/w. to calculate die temperature, use the proper thermal resistance number for the desired package and add in worst-case ambient temperature: t j = t a + ja (p tot ) with the so-8 package ( ja = 120 c/w), at an ambient temperature of 70 c, t j = 70 + 120 (0.37) = 114.4 c die temperature is highest at low input voltage, so use lowest continuous input operating voltage for thermal calculations.
24 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u positive-to-negative converter the circuit in figure 18 is a classic positive-to-negative topology using a grounded inductor. it differs from the standard approach in the way the ic chip derives its feedback signal, however, because the lt1376 accepts only positive feedback signals, the ground pin must be tied to the regulated negative output. a resistor divider to ground or, in this case, the sense pin, then provides the proper feedback voltage for the chip. output** 5v, 0.5a input 4.5v to 20v 1375/76 f18 c2 0.1 f c c r c d2 1n5818 c1 100 f 10v tant c3 10 f to 50 f d1 1n4148 l1* 5 h boost lt1376-5 v in v sw sense gnd v c * increase l1 to 10 h or 20 h for higher current applications. see applications information ** maximum load current depends on minimum input voltage and inductor size. see applications information + + figure 18. positive-to-negative converter inverting regulators differ from buck regulators in the basic switching network. current is delivered to the output as square waves with a peak-to-peak amplitude much greater than load current . this means that maximum load current will be significantly less than the lt1376? 1.5a maximum switch current, even with large inductor values . the buck converter in comparison, delivers current to the output as a triangular wave superimposed on a dc level equal to load current, and load current can approach 1.5a with large inductors. output ripple voltage for the positive- to-negative converter will be much higher than a buck converter. ripple current in the output capacitor will also be much higher. the following equations can be used to calculate operating conditions for the positive-to-negative converter. maximum load current: i i vv vvfl vv vv vv max p in out out in out in out in out f = ? ()( ) + ()()() ? ? ? ? ? ? ? ? () ? () + ? () + () 2 05 05 . . i p = maximum rated switch current v in = minimum input voltage v out = output voltage v f = catch diode forward voltage 0.5 = switch voltage drop at 1.5a example: with v in(min) = 4.7v, v out = 5v, l = 10 h, v f = 0.5v, i p = 1.5a: i max = 0.52a. note that this equation does not take into account that maximum rated switch current (i p ) on the lt1376 is reduced slightly for duty cycles above 50%. if duty cycle is expected to exceed 50% (input voltage less than output voltage), use the actual i p value from the electrical characteristics table. operating duty cycle: dc vv vvv out f in out f = + ? ++ 03 . (this formula uses an average value for switch loss, so it may be several percent in error.) with the conditions above: dc = + ? ++ = 505 47 03 5 05 56 . .. . % this duty cycle is close enough to 50% that i p can be assumed to be 1.5a. output divider if the adjustable part is used, the resistor connected to v out (r2) should be set to approximately 5k. r1 is calculated from: r rv out 1 2242 242 = ? () . .
25 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u inductor value unlike buck converters, positive-to-negative converters cannot use large inductor values to reduce output ripple voltage. at 500khz, values larger than 25 h make almost no change in output ripple. the graph in figure 19 shows peak-to-peak output ripple voltage for a 5v to 5v con- verter versus inductor value. the criteria for choosing the inductor is therefore typically based on ensuring that peak switch current rating is not exceeded. this gives the lowest value of inductance that can be used, but in some cases (lower output load currents) it may give a value that creates unnecessarily high output ripple voltage. a com- promise value is often chosen that reduces output ripple. as you can see from the graph, large inductors will not give arbitrarily low ripple, but small inductors can give high ripple. inductor size ( h) 0 output ripple voltage (mv p-p ) 150 120 90 60 30 0 20 1375/76 f19 5 10 15 25 5v to 5v converter output capacitor esr = 0.1 ? i load = 0.25a i load = 0.1a figure 19. ripple voltage on positive-to-negative converter the difficulty in calculating the minimum inductor size needed is that you must first know whether the switcher will be in continuous or discontinuous mode at the critical point where switch current is 1.5a. the first step is to use the following formula to calculate the load current where the switcher must use continuous mode. if your load current is less than this, use the discontinuous mode formula to calculate minimum inductor needed. if load current is higher, use the continuous mode formula. output current where continuous mode is needed: i vi vv vv v cont in p in out in out f = ()() + () ++ () 22 4 minimum inductor discontinuous mode: l vi fi min out out p = ()() ()( ) 2 2 minimum inductor continuous mode: l vv fv v i i vv v min in out in out p out out f in = ()( ) () + () ? + + () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 21 for the example above, with maximum load current of 0.25a: ia cont = ()( ) + () ++ () = 515 4555505 037 22 . . . this says that discontinuous mode can be used and the minimum inductor needed is found from: lh min = ()( ) ? ? ? ? () = 25 025 500 10 1 5 22 3 2 . ? . in practice, the inductor should be increased by about 30% over the calculated minimum to handle losses and variations in value. this suggests a minimum inductor of 3 h for this application, but looking at the ripple voltage chart shows that output ripple voltage could be reduced by a factor of two by using a 15 h inductor. there is no rule of thumb here to make a final decision. if modest ripple is needed and the larger inductor does the trick, go for it. if ripple is noncritical use the smaller inductor. if ripple is extremely critical, a second filter may have to be added in any case, and the lower value of inductance can be used. keep in mind that the output capacitor is the other critical factor in determining output ripple voltage. ripple shown on the graph (figure 19) is with a capacitor esr of 0.1 ? . this is reasonable for an avx type tps ??or ??size
26 lt1375/lt1376 13756fd applicatio n s i n for m atio n wu u u surface mount solid tantalum capacitor, but the final capacitor chosen must be looked at carefully for esr characteristics. ripple current in the input and output capacitors positive-to-negative converters have high ripple current in both the input and output capacitors. for long capacitor lifetime, the rms value of this current must be less than the high frequency ripple current rating of the capacitor. the following formula will give an approximate value for rms ripple current. this formula assumes continuous mode and large inductor value . small inductors will give somewhat higher ripple current, especially in discontinu- ous mode. the exact formulas are very complex and appear in application note 44, pages 30 and 31. for our purposes here i have simply added a fudge factor (ff). the value for ff is about 1.2 for higher load currents and l 10 h. it increases to about 2.0 for smaller inductors at lower load currents. capacitor ff i v v out out in i rms = ()( ) ff = fudge factor 1 (1.2 to 2.0) diode current average diode current is equal to load current. peak diode current will be considerably higher. 1 normally, jamoca almond peak diode current: continuous i vv v vv lfv v discontinuous v lf out in out in in out in out out mode mode = 2i out = + () + ()( ) ()() + () ()( ) ()() 2 keep in mind that during start-up and output overloads, average diode current may be much higher than with normal loads. care should be used if diodes rated less than 1a are used, especially if continuous overload conditions must be tolerated. dual output sepic converter the circuit in figure 20 generates both positive and negative 5v outputs with a single piece of magnetics. the two inductors shown are actually just two windings on a standard coiltronics inductor. the topology for the 5v output is a standard buck converter. the 5v topology would be a simple flyback winding coupled to the buck converter if c4 were not present. c4 creates the sepic (single-ended primary inductance converter) topology which improves regulation and reduces ripple current in l1. for details on this circuit see design note 100. boost lt1376-5 v in output 5v output ?v ? * l1 is a single core with two windings coiltronics #ctx10-2p ** avx tpsd107m010 ? if load can go to zero, an optional preload of 1k to 5k may be used to improve load regulation input 6v to 25v gnd 1375/76 f20 c2 0.1 f c c 0.01 f r c 470 ? d1 1n5818 c1** 100 f 10v tant c5** 100 f 10v tant c3 22 f 35v tant c4** 100 f 10v tant d2 1n914 d3 1n5818 l1* 10 h l1* v sw sense bias gnd shdn v c + + + + figure 20. dual output sepic converter
27 lt1375/lt1376 13756fd n8 1002 .065 (1.651) typ .045 ?.065 (1.143 ?1.651) .130 .005 (3.302 0.127) .020 (0.508) min .018 .003 (0.457 0.076) .120 (3.048) min 12 3 4 87 6 5 .255 .015* (6.477 0.381) .400* (10.160) max .008 ?.015 (0.203 ?0.381) .300 ?.325 (7.620 ?8.255) .325 +.035 ?015 +0.889 0.381 8.255 () note: 1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio n u n8 package 8-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) so8 0303 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc 1 2 3 4 .150 ?.157 (3.810 ?3.988) note 3 8 7 6 5 .189 ?.197 (4.801 ?5.004) note 3 .228 ?.244 (5.791 ?6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
28 lt1375/lt1376 13756fd related parts part number description comments lt1370 high efficiency dc/dc converter 42v, 6a, 500khz switch lt1371 high efficiency dc/dc converter 35v, 3a, 500khz switch lt1372/lt1377 500khz and 1mhz high efficiency 1.5a switching regulators boost topology lt1374 high efficiency step-down switching regulator 25v, 4.5a, 500khz switch lt1375/lt1376 1.5a step-down switching regulators 500khz, synchronizable in so-8 package lt1507 1.5a step-down switching regulator 500khz, 4v to 16v input, so-8 package lt1576 1.5a step-down switching regulator 200khz, reduced emi generation lt1578 1.5a step-down switching regulator 200khz, reduced emi generation lt1616 600ma step-down switching regulator 1.4mhz, 4v to 25v input, sot-23 package lt1676/lt1776 wide input range step-down switching regulators 60v input, 700ma internal switches ltc1735 high efficiency synchronous step-down, n-ch drive burst mode operation, 16-pin narrow ssop ltc1735-1 high efficiency step-down controller with power good output fault protection, 16-pin ssop and so-8 lt1767 1.5a, 1.4mhz step-down dc/dc converter higher current, 8-lead msop package ltc1772 constant frequency step-down controller in sot-23 higher current, high effieciency: up to 94% ltc1779 0.25a micropower step-down in sot-23 lower current, 100% duty cycle ltc1877 high efficiency monolithic step-down regulator 550khz, ms8, v in up to 10v, i q =10 a, i out to 600ma at v in = 5v ltc1878 high efficiency monolithic step-down regulator 550khz, ms8, v in up to 6v, i q = 10 a, i out to 600ma at v in = 3.3v ltc3404 1.4mhz high efficiency, monolithic synchronous step-down up to 95% efficiency, 100% duty cycle, iq = 10 a, regulator v in = 2.65v to 6v burst mode is a registered trademark of linear technology corporation. lt 0306 rev d ?printed in usa ? linear technology corporation 1995 package descriptio n u s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) 1 n 2 3 4 5 6 7 8 n/2 .150 ?.157 (3.810 ?3.988) note 3 16 15 14 13 .386 ?.394 (9.804 ?10.008) note 3 .228 ?.244 (5.791 ?6.197) 12 11 10 9 s16 0502 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc .245 min n 123 n/2 .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)

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